Pillar-type transistors (vertical transistors) may have desirability in terms of size and scalability. In such pillar-type transistors, diffusion layers comprising sources and drains are formed at upper and lower portions of pillars, and channels are formed between the sources and the drains within the pillars. Bitlines may be disposed on lower portions of pillar-type transistors for utilization in memory (e.g., dynamic random access memory (DRAM)).
There is a continuing goal to improve architectural layouts of integrated circuit structures in an effort to maintain acceptable electrical connections between components while achieving ever higher levels of integration. It is desired to improve architectural characteristics of pillar-type transistors.